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* only hw script works for now added verification interfaces and update makefile for vcs runs vcs runs fixes added dump.tcl Refactored puf_core * fixed code style * added common PUF_DATA_WIDTH parameter * marked all parameters as int * fixed all verilator warnings Fixed verilator waveform flags + added .vlt file Edited .gitignore Moved /bd to .gitignore Fixed verilog parameter type int -> integer Atomated project creation, hw copying, synthesis and strategy applying Applied skip utilization check parameter Added current commit hash to NAME_OF_RUN variable for saving artifacts For NAME_OF_RUN, handled the case when the repo has no commits or git inited Added some README Improved script for retrieving part of commit hash * With this change, Makefile won't fail even with .git folder removed, or if it has zero commits Added make target for copying firmware * Also changed NAS folder structure a bit, so that now artifacts have their own folder * Added a few more files of the firmware Added Makefile target to program the board * The changes also include `read_example` target for tests and future improvement Minor Makefile improvements Fixed vivado's project refreshing after changing some files Updated the documentation Added all PYNQs' ips, added experiment target added stand cro rtl upd tb coctb env upd + rtl fixed puf_core control logic update ru added lut6 model update gates Implemented timing sim build (script generation) Splitted make targets, added python and LAB402_FPGA define Added logging to post implementation timing run Updated frequency measuring testbench Added timing_sim targets (with sdf changes) and defines via tcl and verilog header Fixed CFGs for gates, fixed lut types, fixed I/O for some gates Updated .TCL scripts (fixed defines, improved styling) Fixed I/O usage of some modules Added unit tests and updated testbenches for cro Fixed I/O ports, removed buffer, fixed attributes Improved timing verification targets and updated the documentation sram experiments: dead pynq PL programming added sram & ld puf upd added ld metastable array upd ctrl logic in ld Removed unnecessary files
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